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42062a?led?02/2013 features ? dual-string led driver for 2-color or unequal vf leds ? pwm dimming with 180 phase shift of led strings ? programmable look-up table for color temperature compensation ? main led string driven by linear current controller ? drives external n-channel mosfet ? 3% current accuracy , no ripple current ? adaptively controls headro om of both ac/dc and dc/dc, isolated or non-isolated topology ? wide pwm dimming range with 12-bit precision ? 8-bit dac for peak current control ? color-adjust led string uses floating buck controller ? drives external n-channel mosfet ? temperature color compensation using programmable look-up table ? over 100:1 dimming range with 8-bit precision ? 8-bit dac allows changing current sense threshold ? open and short led protection ? over-temperature fault detection ? operates stand-alone or with a microcontroller ? open-drain fault indicator output ? -40c to +105c operating temperature range typical applications ? general and architectural lamps ? high cri led fixtures ? down lights and recessed lights ? par lamps atmel led drivers msl2021 2-string led driver with built-in color temperature compensation and adaptive h eadroom control for high cri led luminaires
2 msl2021 [datasheet] 42062a?led?02/2013 1. introduction the msl2021 led driver for two-color systems includes a linear cu rrent controller for the main string, typically for white leds, and a second floating buck controller for a color-adjust led string. both the switching and linear controllers drive external mosfets to provide flexibility over a wi de range of power levels (led currents and voltages). the msl2021 adaptively manages the voltage powering the main led string. a proprietary and patent pending efficiency optimizer (eo) algorithm controls the volt age output of both ac/dc and dc/dc, isolated or non-isolated topology, including ultra-low bandwidth single-stage pfc flyback controller. the msl2021 features peak current control and individual st ring pwm dimming, with the two strings driven at a 180 ?? out of phase. the main led string?s current is ripple-free and has very high accuracy. the pwm dimming frequency for both leds strings is 400hz to give a predictable and wide di mming range. a thermistor connection allows automatic compensation of luminous efficacy in a two-color led fixtur e to maintain consistent color balance across temperature. the msl2021 operates from 9.5v to 15v input. the color-adjus t string voltage regulation loop uses a constant off-time control algorithm to achieve stable control with good transient behavior. for flexibility of design, off-time is set with an external resistor. led current in both the strings can be adjusted using internal 8-bit dacs. the internal registers are i 2 c accessible. integrated non-volatile eeprom memory, also accessed through the i 2 c serial interface, allows configuration at final test in case that the factory default settings need to be modified. the msl2021 is available in the space-saving 24-pin 4x 4mm qfn package and operate over the extended -40c to 105c operating range. 2. ordering information note: 1. lead-free, halogen-free, rohs compliant package 3. application circuit ordering code description package (1) msl2021in two string led driver 4 x 4mm 24-pin qfn single stage pfc flyback controller fbo a c mains white led string color led string bridge rectifier & emi filter ntc thm d g s drv cs msl2021 led driver linear led driver mcu floating buck led driver pwm1 vdd v in
3 msl2021 [datasheet] 42062a?led?02/2013 4. absolute maximum ratings voltage with respect to agnd avin, pvin, en -0.3v to +16.5v vcc, pwm, fltb, sda, scl, toff, rext, fbo -0.3v to +5.5v vdd -0.3v to +2.75v thm -0.3v to vcc+0.3v cs, s -0.3v to vdd+0.3v d -0.3v to +22v g, d rv -0.3v to vin+0.3v pgnd, agnd -0.3v to +0.3v current (into pin) avin, pvin, drv, g (average) 100ma pvin (peak, =1% duty) 1a drv, g (peak, =1% duty) 1a pgnd (peak, =1% duty) -1a agnd, pgnd (average) -100ma all other pins 10ma continuous power dissipation at 70c 24-pin 4mm x 4mm vqfn (derate 21.8mw/c above ta = +70c) 1200mw ambient operating temperature range -40c to +105c junction temperature +125c storage temperature range -65c to +125c lead soldering temperature, 10s +300c
4 msl2021 [datasheet] 42062a?led?02/2013 5. electrical characteristics avin = pvin = 12v, -40c t a 105c, typical operating circuit, unless otherwise noted. typical values at t a = +25c. table 5-1. dc electrical characteristics parameter conditions min. typ. max. unit avin, pvin operating supply voltage 9.5 12 15 v avin operating supply current leds on at pwm = 100%, serial interface idle 10 ma avin idle supply current en = sleep = 1, all digital inputs = 0 7 10 ma pvin idle supply current en = sleep = 1, all digital inputs = 0 0 a avin disable supply current v en = 0, all digital inputs = 0 5 a vcc regulation voltage i vcc = 10ma peak (7) 4.5 5 5.5 v vdd regulation voltage i vdd = 10ma peak (7) 2.25 2.5 2.75 v pwm, pwm1, pwm2, scl, sda input high voltage 0.7 ? v vdd v pwm, pwm1, pwm2, scl, sda input low voltage 0.3 ? v vdd v en input high voltage 2 v en input low voltage 0.5 v en input hysteresis 100 mv sda, fltb output low voltage sinking 6ma 0.3 v scl, sda, pwm, pwm1, pwm2, fltb leakage current -5 5 ? a s current sense regulation voltage t a = 25 ? c, mref = 0x64 194 200 206 mv s current sense regulation voltage accuracy main string at 100% duty cycle, t a = 25 ? c, mref = 0x64 -3 +3 % s current sense regulation voltage temperature coefficient -220 ppm/oc g maximum output voltage avin ? 3.5 9.5 avin ? 2.0 v d regulation threshold eoctrl = 0xe5 0.9 1 1.1 v cs current sense regulation voltage caref = 0x64 200 mv drv impedance v drv = 12v, i drv = 20ma 5.6 9 ? v drv = 0v, i drv = -20ma 5.6 9 ? fbo full scale current 170 255 340 a
5 msl2021 [datasheet] 42062a?led?02/2013 table 5-2. ac electrical characteristics table 5-3. i 2 c switching characteristics notes: 1. minimum scl clock frequency is limited by the bus timeout feature, which resets the serial bus interface when either sd a or scl is held low for t timeout . 2. sda data valid acknowledge time is scl low to sda (out) low acknowledge time. 3. sda data valid time is minimum sda output data-valid time following scl low transition. 4. a master device must internally provide an sda hold time of at least 300ns to ensure an scl low state. fbo lsb current 1.0 ? a thm source current 100 ? a thm voltage range 0 1.5 v thermal shutdown temperature temperature rising 133 c thermal shutdown hysteresis 15 c parameter conditions min. typ. max. unit drv t off timing r toff = 45.3k ? 0.5 ? s pwm input frequency (8) 60 10,000 hz pwm duty cycle 1 100 % pwm duty cycle resolution msl2021 0.4 % parameter symbol conditions min. typ. max. unit scl clock frequency (1) 0.05 1,000 khz stop to start condition bus free time t buf 0.5 s repeated start condition hold time t hd:sta 0.26 s repeated start condition setup time t su:sta 0.26 s stop condition setup time t su:stop 0.26 s sda data hold time t hd:dat 5 ns sda data valid acknowledge time (2) 0.05 0.55 s sda data valid time (3) 0.05 0.55 s sda data set-up time t su:dat 100 ns scl clock low period t low 0.5 s scl clock high period t high 0.26 s sda, scl fall time t f (4)(5) 120 ns sda, scl rise time t r 120 ns sda, scl input suppression filter period (6) 50 ns bus timeout t timeout (1) 25 ms parameter conditions min. typ. max. unit
6 msl2021 [datasheet] 42062a?led?02/2013 5. the maximum sda and scl rise times is 300ns. the maximum sda fall time is 250ns. this allows seri es protection resistors to b e connected between sda and scl inputs and the sda/scl bus lines without exceeding the maximum allowable rise time. 6. includes input filters on sda and sc l that suppress noise less than 50ns. 7. additional decoupling may be required when pulling current from vcc and/or vdd in noisy environments. 8. 2s minimum on time for main led string pwm dimming. typical operating characteristics figure 5-1. start-up behavior, pwm = 10% duty cycle (test conditions). figure 5-2. start-up behavior, pwm = 90% duty cycle (test conditions). v led i in i main fbo v led i in i main fbo
7 msl2021 [datasheet] 42062a?led?02/2013 figure 5-3. normal operation, pwm = 10% duty cycle (test conditions). figure 5-4. normal operation, pwm = 90% duty cycle (test conditions). pwm in i ca i main pwm in i ca i main
8 msl2021 [datasheet] 42062a?led?02/2013 figure 5-5. fault response, string open circuit (test conditions). figure 5-6. fault response, led short circuit (test conditions). pwm in i ca i main fltb pwm in i ca i main fltb
9 msl2021 [datasheet] 42062a?led?02/2013 figure 5-7. input current vs. input voltage figure 5-8. average led current vs. input pwm duty cycle 0.0001 0.001 0.01 0.1 1 10 100 10 11 12 13 14 15 i in (ma) v in (v) f in = 400hz pwm = 50% i in i sleep i shdn 0 20 40 60 80 100 0 50 100 led current (%fs) duty cycle (%) f in = 400hz main string
10 msl2021 [datasheet] 42062a?led?02/2013 figure 5-9. v cc and v dd regulation 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 20406080100 v out (v) i out (ma) f in = 400hz pwm = 50% vcc vdd
11 msl2021 [datasheet] 42062a?led?02/2013 6. block diagram figure 6-1. msl2021 block diagram regulators avin rext 1.2v current generator g s dac adc pwm efficiency optimizer fbo drv c off s r q qb vref cs control logic en fault detect fltb toff current generator oscillator d vcc vdd pvin mux dac start clock vref pwm digitizer thm 400hz pwm generator and duty cycle engine vref pgnd agnd look-up table eeprom sdcr register
12 msl2021 [datasheet] 42062a?led?02/2013 7. pinout and pin description 7.1 pinout msl2021 7.2 pin descriptions 1 2 3 4 5 6 18 17 16 15 14 13 7 8 9 10 11 12 24 23 22 21 20 19 fbo en pwm scl sda fltb s nc pvin drv pgnd cs vdd agnd vcc avin d g nc thm rext toff dnc cgnd msl2021 (top view) name pin description fbo 1 feedback output feedback output from efficiency optimizer. c onnect fbo to the led power supply regulation feedback node to control v led . when unused connect fbo to vcc. en 2 enable input (active high) drive en high to turn on the msl2021, drive en low to turn it off. for automatic start-up connect en to avin. pwm 3 pwm dimming input drive pwm with a pulse-width modulated si gnal to control led brightness. see ?pwm and led brightness? on page 20 for details. scl 4 serial clock input scl is the i2c serial interface clock input. see ?i2c serial interface ? on page 31 details. sda 5 serial data input/output sda is the i2c serial interface data i/o. see ?i2c serial interface ? on page 31 details. fltb 6 fault output (open drain, active low) fltb sinks current to agnd when a fault condition exists. toggle en low then high to clear fltb, or clear faults through the serial interface (see ?fault status register (faultstat, 0x23), read only? on page 29 ). use the serial interface to access fault information and to enable/disable fault response.
13 msl2021 [datasheet] 42062a?led?02/2013 nc 7, 17 no internal connection thm 8 ntc thermistor sensing input connect a negative temperature coefficient thermist or (ert-j0eg103fa or equivalent) from thm to agnd, in series with a 1.5k ? resistor. locate the thermistor close to the color-adjust leds to monitor their temperature. this allows the msl2021 to automatically temperature compensate the color- adjust string brightness. rext 9 external resistor connect a 46.4k ? , 1% resistor from rext to agnd. toff 10 off-time set input a resistor from toff to agnd controls the constant off time for the color-adjust string floating buck converter, where r toff = t off ? (90.9 x 10 9 ), with t off in seconds and r toff in ohms. for example, an off time of 0.5 ? s results in a resist or value of 45.3k ? (to the nearest 1% value). dnc 11 do not connect do not make external connection to dnc. cgnd 12 connect to ground connect cgnd to agnd. cs 13 current sense input for th e color-adjust string connect cs to the external current sense resist or of the color-adjust string. the current sense threshold is 200mv. pgnd 14 power ground pgnd is the ground connection for the fet gate drivers. connect pgnd to agnd close to the msl2021. drv 15 gate drive for color-adjust (floating buck regulator) mosfet connect drv to the gate of the external power mosfet. pvin 16 power voltage input pvin powers drv, the floating buck fet gate driver . bypass pvin to pgnd with a 1.0f or greater capacitor. s 18 source sense input for main led string mosfet connect s to the source of the external mosfet, an d to the current sense resistor for the main led string. the current sense threshold is 200mv. g 19 gate output for ma in string mosfet connect g to the gate of the main string external mosfet. d 20 drain output for main string mosfet connect d to the drain of the main string external mosfet. avin 21 analog voltage input avin is the power input to the msl2021. bypass av in to agnd with a 1.0f or greater capacitor placed close to avin. vcc 22 5v internal voltage connect 10uf bypass capacitor from vcc to agnd. agnd 23 analog ground connect agnd to system ground. vdd 24 2.5v internal voltage connect 10uf bypass capacitor from vdd to agnd. ep ep exposed pad ep is the main thermal path for heat to escape the die. connect ep to a large copper plane connected to pgnd and agnd. name pin description
14 msl2021 [datasheet] 42062a?led?02/2013 8. typical application circuit msl2021 controlling the output of an isolated pfc controller; a linear current sink regulates the white led string current and a floating buck converter regulates the color led string current. figure 8-1. typical application circuit 9. detailed description the msl2021 drives two led strings, the main string and the co lor-adjust string. the main string leds are typically white and used to provide accurate light intensity control.the color-adjust string leds are used to control the color temperature. the combined light output is a blended high cr i light, for example, than what white leds can alone produce. the main string is directly controlled by a puls e width modulated (pwm) constant current controller (current sink to ground). an efficiency optimizer (eo) output controls the main string voltage, via feed-back to the led string power supply, to minimize the voltage across t he led current controller, minimizing power loss. the color-adjust string is regulated by a floating buck controller. the buck controller converts the voltage of the main string?s supply to a voltage appropriate for the color-adjus t leds. additionally, the msl 2021 has a programmable 8-bit registers that allows adjustment of the current by changing the source feedback reference voltages (see ?block diagram? on page 11 ). g drv avin 12v agnd ac-dc isolated with pfc sda scl configuration interface msl2021 led driver rext cs pwm pwm + - 0.56 thm ert- j0eg103fa fltb fault fbo en en white leds color leds pgnd vac r top r bottom 820h d pvin vcc vdd toff s (optional) 46.4k 45.3 k 10f 10uf 1f 1f 0.56 100k 1f 1.50k q1 q2 d1
15 msl2021 [datasheet] 42062a?led?02/2013 10. fault conditions the msl2021 detects fault conditions, and takes corrective action when faults are verified. string open circuit and led short circuit conditions of the co lor-adjust string are monitored. when one of these faults occurs, fltb pulls low to indicate a fault condition and the color-adjust leds turn off. read fault status register 0x23 to determine the fault type. clear these faults by toggling en low then high. faults that persist re-establish the fault response. mask string faults using fault disable register 0x22. for the main led string, when an open led occurs, the voltage of the ac/dc or dc/dc input power supply reaches the maximum allowed. over-temperature protection puts the device to sleep when the die temperature is above 133 ? c. the device turns back on when the die temperature falls below 118 ? c, and normal operation resumes. while asleep, the i 2 c interface remains active; see ?fault disable regist er (fault, 0x22)? and ?fault status register (faultstat, 0x23), read only? on page 29 for more information about thermal shutdown. table 10-1. fault conditions, response and recovery 11. applications information 11.1 turn-on sequence the msl2021 waits for 250ms after power is applied to allow the ac/dc or dc/dc input supply to establish the default voltage. then the msl2021 starts to optimize the led string voltage (v led ), and then starts to drive the led strings. it is critical that the ac/dc or dc/dc converter that powers t he led strings reaches its nominal output voltage in less than 250ms after power is applied. when the 250ms start-up delay is complete, the efficiency optimizer adjusts the led voltage to the proper level to drive the main string. after the voltage is set, normal pwm operation begins for both the main and color-adjust strings. this turn-on sequence allows the light to come up at the proper color and intensity without flashing or flicker. 11.2 setting the main st ring current with r s the main string led on-current regulates by monitoring the volt age at the s pin, the main string mosfet source resistor connection. the default feedback voltage at the s pin is 200mv. choose the string current sense resistor r s using: where i led is the main string regulation current. the main st ring reference voltage (mref) register 0x20 sets the feedback voltage, to 200mv, at 2mv per lsb. the regulation voltage, v s(fb) , is: fault response recovery action die temperature > 133 ? c asleep (i 2 c still active) when die temperature falls below 118 ? c operation resumes as if en is pulled high color-adjust string has shorted leds color-adjust string turns off, fltb pulls low, and bit 0 of the fault status register 0x23 sets high correct the short condition in led string. toggle en low to high to resume operation color-adjust string is open circuit color-adjust string turns off, fltb pulls low, and bit 1 of the fault status register 0x23 sets high correct the open condition in led string. toggle en low to high resume operation r s 0.2 i led ----------- - ? =
16 msl2021 [datasheet] 42062a?led?02/2013 where mref is the decimal equivalent of the value in register 0x20. the default value for mref is 0x64, for a feedback voltage of 0.2v. change the feedback voltage by changing the value in register 0x20 using the serial interface. led average current is within 3% of the targeted value when a 1% resistor is used for r s . 11.3 setting ac/dc output voltage the efficiency optimizer output, fbo, connects to the ac /dc or dc/dc converter?s output voltage feedback node, and pulls current from the node to force the converter?s output voltage up. the msl2021 works with any input power converter topology that uses a resistor divider to set its output voltage. operation with a ac/dc pfc converter is described below. select the two resistors that set the nominal ac/dc led power supply?s output voltage by first determining the minimum output voltage using: where v fmin is the minimum led forward voltage for the main string leds at the expected led current, n is the number of leds in the string, and 0.2v is the minimum overhead required for the current sense resistor and the fet. then determine the maximum output voltage using: where v fmax is the maximum led forward voltage for the main string leds at the operating led current, n is the number of leds in the string, and 1.2v is the maximum overhead required for the current sense resistor and the fet. determine the value for the upper voltage setting resistor using: where 170 ? a is the minimum fbo full scale current. determine the lower resistor using: where v fb is the feedback regulation voltage of the switch mode converter. 11.4 selecting the main string mosfet the main string mosfet sinks the string current to ground through current sense resistor r s . output of pin g drives the gate of the mosfet at up to vin - 2v. select a mosfet with a maximum drain-source voltage of at least 20% above: where 340a is the maximum fbo full scale current. 11.5 selecting the drain resistor ? r d the drain resistor, r d , connects the msl2021 to the drain of the main string external mosfet. use a 100k ? for r d . v sfb ?? 0.002 mref ? ?? v = v out min ?? v fmin ?? n ?? 0.2 v + ? ? v out max ?? v fmax ?? n ?? 1.2 v + ? = r top v out max ?? v out min ? ?? ? 170 10 6 ? ? ---------------------------------------------------------------- - ? ? r bottom r top v fb v out min ?? v fb ? ------------------------------------------- - ? ? = v fb r top r bottom ------------------------ 1 + ?? ?? 340 ? ar top ? +
17 msl2021 [datasheet] 42062a?led?02/2013 11.6 selecting the color-adjust string floating buck components figure 11-1. floating buck led driver the msl2021 includes a driver for a constant off-time floating buck topology, shown in figure 11-1 , to convert the main string voltage to a value appropriate for the color-adjust led string. the buck is operated in continuous conduction mode. continuous conduction operation is assured when t he peak-to-peak ripple current in the inductor, ? i l , is less than twice the average led current. a peak-to-peak ripple current magnit ude of 15% of the average led on-current is suggested, i.e. a where i ave is the average color-adjust led string on-current. choose i ave appropriate for the color-adjust leds ( figure 11-1 on page 17 and figure 11-2 on page 18 ) and calculate the peak string on-current using a drv cs r cs color leds (color-adjust string) l o v led d 1 toff r toff c o c i q pgnd v buck + - white leds (main string) i ave msl2021 led driver ? i l 0.15 i ave ? i peak i ave ? i l 2 -------- + =
18 msl2021 [datasheet] 42062a?led?02/2013 figure 11-2. color-adjust string led on-current details. the color-adjust string led on-current regulates by monito ring the voltage at cs, the color-adjust string fet source resistor connection. the reference voltage v csfb for cs is 200mv ( v csfb is 200mv by default, and is adjustable through the serial interface; see the register definitions for details about changing v csfb ). choose the current sense resistor r cs using determine v buck , the voltage across the color-adjust leds, using v where n is the number of leds in the string and v f is the forward voltage drop of the leds at i peak . the duty ratio of mosfet q is where v led is the main string voltage, figure 11-1 on page 17 . the constant off-time of the mosfet is t off and calculated in seconds using s where f s is the selected switching frequency in hz. use 100khz to 1mhz for f s . set t off with resistor r toff from toff to gnd ( figure 11-1 on page 17 ), whose value is choose the inductor value using h use a ferrite inductor with a saturation current at least 50% higher than the peak current flowing in it: a note here a particular advantage of constant off-time operation of the buck converter is that ripple current is independent of the input voltage. the circuit prov ides a constant average led current, i ave , but the buck converter actually regulates the peak inductor current, i peak ( figure 11-1 on page 17 and figure 11-2 on page 18 ). from the equation for the inductor value l 0 above, we see that because t off is constant, and v buck is relatively constant, the ripple current ? i l is also constant, so that i ave is a constant, as desired. if the main string voltage changes, the switching frequency changes to keep the on-time constant, thus the ripple current is independent of the input voltage. i peak i ave inductor current led current (when using c o ) t off t i ?i l r cs v csfb i peak ---------------- ? = v buck nv f = d v buck v led ----------------- = t off 1 d ? f s ------------ - = r t off t off 90.9 10 9 ? ??? = l o v buck t off ? ? i l ----------------------------- - = i l sat 1.5 i peak ? ?
19 msl2021 [datasheet] 42062a?led?02/2013 this topology does not require an output capacitor, c o in figure 11-1 on page 17 . when used, c o steers the inductor?s ripple current away from the leds but reduces the accuracy of pwm dimming because the voltage across it cannot change quickly. when using c o , a ceramic capacitor of between 1.0f and 10f is adequate, with a voltage rating higher than v buck . the output capacitor of the ac/dc converter that produces the main string voltage, c i in figure 11-1 on page 17 , doubles as the buck?s input capacitor. the capacitor?s function is to provide a smooth voltage to the buck converter. it should be able to handle the r.m.s. ripple current of the buck converter, which is approximately equal to a this ripple current peaks at a duty ratio of d = 0.5. select an n-channel mosfet for q with a maximum drain-source voltage at least 25% above v led . the r.m.s. current in the mosfet is approximately equal to a the mosfet conduction power loss due to this current is w where r ds is the hot on-resistance of the mosfet, which can be found in the mosfet datasheet, and is typically 1.5 to 1.8 times greater than the cold resistance. the mosfet wil l also incur switching losses, which can be difficult to calculate exactly. a good rule-of-thumb is to choose a mo sfet in a package that dissipates at least four times p con . the average current in the output rectifier d 1 is a and the power dissipated in the rectifier due to conduction is w where v on is the voltage drop across the rectifier at the forward current of i d1 . pick a rectifier with an average current rating at least 50% higher than i d1 . use a schottky rectifier if the led voltage is less than 50v. the schottky rectifier?s voltage rating should be at least 25% higher than v led . schottky rectifiers have very low on-state voltage and very fast switching speed, but at high voltage and high temperatures their leakage current becomes significant. the power dissipated in the schottky rectifier due to the leakage current at any temperature and duty ratio is w where i r is the reverse leakage current, found in the diode?s datasheet. this power must be added to the conduction power loss. w make sure that the rectifier?s total power dissipation is within the rectifier?s specifications. i c i i ave d 1 d ? ?? = i q i ave d = d r i r i p ds ave ds q con 2 2 ? ? i d i i ave 1 d ? ?? = p con d 1 i d 1 v on = p lkg v led i r d = p d 1 p con d p lkg + =
20 msl2021 [datasheet] 42062a?led?02/2013 11.7 pwm and led brightness the ?block diagram? on page 11 shows how the msl2021 controls the brightness of the leds. the duty cycle of the main string equals the duty cycle of the input signal at pwm. the pwm input accepts an input signal frequency of 60hz to 10khz, while the led dimming frequency, of both the main and color-adjust strings, is 400hz. the duty cycle of the color-adjust string is based on the duty cycle of the signal at the pwm input, but compensated for temperature based on a programmable look-up table, whose defaults are presented in table 11-2 on page 21 . see ?light color and the thm input? on page 20 for temperature adjustment information. figure 11-3. led current and duty cycle control. 11.8 light color and the thm input the overall color of the light generated by the two led strings is a blend of the main string?s white leds and the color- adjust string?s color leds. brightness is primarily controll ed by the duty cycles of the pwm signals driving the leds. the brightness of white leds is relatively constant over temper ature, but the brightness of color leds may drop significantly as temperature increases. the main string?s pwm duty cycle is fixed at the duty cycle of the input pwm signal, but the duty cycle of the color-adjust string is changed as the led temperature changes, to keep the blended light color constant. the thermistor input, thm, monitors the temperature of an external thermistor connected from thm to ground. a fixed current is forced out thm to generate a voltage that is proporti onal to the thermistor?s temperature. the thm voltage is measured by a 8-bit adc internal to the ms l2021. when used with the suggested thermistor ( ert-j0eg103fa or equivalent ) in series with a 1.5k ? resistor, thm measures temperatures from 18 o c to 80 o c with 2 o c resolution, for 32 different temperature values. when the temperature is below 18 o c, 18 o c is returned by the temperature monitor circuit. when the temperature is above 80 o c, 80 o c is returned by the temperature monito r circuit. the temperature information is fed to the color-adjust string?s duty cycle circuit. g d drv cs s + - + - r d r s r cs pwm pwm engine 400hz clock dac 0x20 dac 0x21 thm thermal monitor en en msl2021
21 msl2021 [datasheet] 42062a?led?02/2013 the msl2021 modifies the color-adjust string duty cycle using a look-up table. default values are presented in table 11- 1 ; each location in the table corresponds to one temperature. the modification value is stored in the table as an 8-bit color-adjust duty cycle ratio (sdcr). the sdcr, a number from 0 to 255, is divided by 255, and multiplied by the duty cycle of the incoming pwm signal. the result is the duty cycle of the color-adjust string. the table is programmable through the serial interface when values different from the defaults are desired. table 11-1. temperature based duty cycle modification of the color-adjust string table 11-2. temperature look-up table defaults (1) part color-adjust duty cycl temperature adjustment limits msl2021 sdcrxx = value in look-up table 0x00 thru 0x1f sdcrxx = 0xff returns 100% of the pwm duty cycle sdcrxx = 0x00 returns 0% of the pwm duty cycle temperature (c) register multiplication factor address name default value 18 0x00 sdcr18 0x4c 0.300 20 0x01 sdcr20 0x4d 0.303 22 0x02 sdcr22 0x4e 0.307 24 0x03 sdcr24 0x4f 0.311 26 0x04 sdcr26 0x50 0.314 28 0x05 sdcr28 0x51 0.318 30 0x06 sdcr30 0x52 0.322 32 0x07 sdcr32 0x53 0.327 34 0x08 sdcr34 0x54 0.331 36 0x09 sdcr36 0x55 0.336 38 0x0a sdcr38 0x56 0.340 40 0x0b sdcr40 0x58 0.345 42 0x0c sdcr42 0x59 0.350 44 0x0d sdcr44 0x5a 0.355 46 0x0e sdcr46 0x5c 0.361 48 0x0f sdcr48 0x5d 0.367 50 0x10 sdcr50 0x5e 0.373 52 0x11 sdcr52 0x60 0.379 54 0x12 sdcr54 0x62 0.385 56 0x13 sdcr56 0x63 0.392 58 0x14 sdcr58 0x65 0.399 dc ca sdcrxx 255 --------------------- - dc pwm ? = sdcrxx 255 --------------------- -
22 msl2021 [datasheet] 42062a?led?02/2013 note: 1. change sdcrxx values through the serial interface figure 11-4. msl2021 default look-up table color correction vs. temperature. 60 0x15 sdcr60 0x67 0.406 62 0x16 sdcr62 0x69 0.414 64 0x17 sdcr24 0x6b 0.422 66 0x18 sdcr66 0x6d 0.431 68 0x19 sdcr68 0x70 0.440 70 0x1a sdcr70 0x72 0.450 72 0x1b sdcr72 0x72 0.460 74 0x1c sdcr74 0x72 0.460 76 0x1d sdcr76 0x72 0.460 78 0x1e sdcr78 0x72 0.460 80 0x1f sdcr70 0x72 0.460 temperature (c) register multiplication factor address name default value sdcrxx 255 --------------------- - 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 020406080100 temperature (oc) duty cycle multiplication factor
23 msl2021 [datasheet] 42062a?led?02/2013 11.9 msl2021 look-up tabl e lockout procedure the msl2021 features a lock for the look-up table. when lo cked, the table?s registers (0x00 through 0x1f) become read- only. a locked table cannot be unlocked; changing the table?s r egisters is no longer possible. reads of a locked table?s registers return 0x00, unless the password (chosen when locking t he table) is first entered to make the registers visible. locking the table requires use of the i 2 c interface to enter data, read data and program the eeprom. for information about using the i 2 c interface, see ?i2c serial interface ? on page 31 . for information about programming the eeprom see ?eeprom address and control/status registers? on page 26 . lock the table by performing the following sequence; an example is presented below: 1. fill the look-up table with data. 2. commit the look-up table to eeprom. 3. cycle power, then verify the contents of the look-up table. 4. choose a 16-bit password. 5. enter the password into password registers 0x68 and 0x69. 6. enter the password into password verification registers 0x38 and 0x39. 7. commit the password to eeprom. 8. set the lock bit. 9. commit the lock bit to eeprom. 10. cycle power to the msl2021. 11.9.1 example: the look-up table is four pages long (each page is 8-bytes) . when the look-up table is filled with the proper data, commit the data to the eeprom, one page at a time, by sending the following commands to the msl2021 through its i 2 c interface: 0x60 0x00 {to register 0x60 write 0x00: sets the eeprom write pointer to 0x00} 0x61 0x04 {to register 0x61 write 0x04: writes the first page (8 bytes) of data to the eeprom} wait 5ms. 0x61 0x00 {to register 0x61 write 0x00 : disables eeprom writing} 0x60 0x08 {sets the eeprom write pointer to 0x08} 0x61 0x04 {writes the second page of data to the eeprom} wait 5ms. 0x61 0x00 {disables eeprom writing} 0x60 0x10 {sets the eeprom write pointer to 0x10} 0x61 0x04 {writes the third page of data to the eeprom} wait 5ms. 0x61 0x00 {disables eeprom writing} 0x60 0x18 {sets the eeprom write pointer to 0x18} 0x61 0x04 {writes the final page of data to the eeprom} wait 5ms.
24 msl2021 [datasheet] 42062a?led?02/2013 0x61 0x00 {disables eeprom writing} the eeprom is now programmed with the data that are in registers 0x00 through 0x1f (t he look-up table). although not required, now is a good time to cycle power to the msl2021, then read registers 0x00 through 0x1f to verify that the eeprom was properly programmed (at power-up the eeprom automatically programs registers 0x00 through 0x40). next, choose a 16-bit password and write it into the password registers, and into the password verification registers. for this example the password is 0xaa55: 0x68 0xaa 0x69 0x55 {writes the password into the password registers 0x68 and 0x69} 0x38 0xaa 0x38 0x55 {writes the same password into t he password verification registers 0x38 and 0x39} now commit the password to eeprom. 0x60 0x68 {sets the eeprom write pointer to 0x68} 0x61 0x03 {writes the first byte of the password to the eeprom} wait 5ms. 0x61 0x00 {disables eeprom writing} 0x60 0x69 {sets the eeprom write pointer to 0x69} 0x61 0x03 {writes the second byte of the password to the eeprom} wait 5ms. 0x61 0x00 {disables eeprom writing} next, set the lock bit and commit it to eeprom. 0x3a 0x02 {sets the lock bit (bit d1) in register 0x3a} 0x60 0x3a {sets the eeprom write pointer to 0x3a} 0x61 0x03 {writes the contents of register 0x3a to the eeprom} wait 5ms. 0x61 0x00 {disables eeprom writing} now cycle power to the msl2021. all reads of the look-up table now return 0x00. to read the table, enter the password into the password verification registers: 0x38 0xaa 0x39 0x55 {writes the password into registers 0x38 and 0x39}
25 msl2021 [datasheet] 42062a?led?02/2013 reads of the look-up table now return its true contents, until the password register is changed, power is cycled or enable input en is toggled. 12. control registers table 12-1. register map (1) notes: 1. do not change the contents of undefined bits or unlisted registers. 2. unless changed through the eeprom, these default values l oad at power-up, and when en is taken from low to high. address and register name function default value (2) bit functions d7 d6 d5 d4 d3 d2 d1 d0 0x00 sdcr18 look up for 18 ? c 0x4c look up table 0x01 sdcr20 look up for 20 ? c 0x4d look up table ?thru? ?thru? 0x1e sdcr78 look up for 78 ? c 0x72 look up table 0x1f sdcr80 look up for 80 ? c 0x72 look up table 0x20 mref main string feedback reference voltage 0x64 ms ref = 2mv per lsb 0x21 caref color-adjust string reference feedback voltage 0x64 v caref = 2mv per lsb 0x22 fault disable color-adjust fault disable 0x00 - - - - - tsdmask ocdis scdis 0x23 faultstat fault status read only - - - - -tsdocfltscflt 0x24 sleep configuration 0x00 - - - - - - - sleep 0x31 temp temperature read only thermistor temperature 0x38 pwv(high) look-up table password verification high byte 0xff look-up table password verification [15:8] 0x39 pwv(low) look-up table password verification low byte 0xff look-up table password verification [7:0] 0x3a lut lock look-up table lock 0x83 - - - - - - lock[1:0] 0x40 eoctrl efficiency optimizer 0xe5 - - - - dthresh[3:0] 0x60 e2addr eeprom address 0x00 - eeprom address pointer 0x61 e2ctrl eeprom control 0x00 - - - - - rwctrl[2:0] 0x68 pw(high) look-up table password high byte 0xff look-up table password [15:8] 0x69 pw(low) look-up table password low byte 0xff look-up table password [7:0]
26 msl2021 [datasheet] 42062a?led?02/2013 12.1 eeprom and power-up defaults an on-chip eeprom holds all the default register values. at power-up the data in the eeprom is transferred directly to control registers 0x00 thru 0x51, setting up the device for operation. any changes made to registers 0x00 thru 0x69 after power-up ar e not reflected in the eeprom and are lost when power is removed from the device, or when the enable input en is forced low. if a different power-up condition is desired program the values into the eeprom via the serial interface as explained in the next section, or contact the factory to inquire about ordering a customized power-up setting. 12.2 eeprom address and c ontrol/status registers the eeprom can be visualized as an image of the control r egisters from 0x00 thru 0x69. change an eeprom register value by writing the new value into the associated control register, and then instructing the device to program that value into the eeprom. two control registers facilitate this pr ocess, the eeprom address register e2addr (0x60), and the eeprom control register e2ctrl (0x61). into e2addr write the location of the data that is to be programmed into the eeprom, and write 0x03 to e2ctrl to command the device to program that data into the eeprom. programming the eeprom takes a finite amount of time; after sending a co mmand to e2ctrl wait 5ms, then end the write cycle by writing 0x00 to e2ctrl. example: change the string current feedback voltage mref to 100mv. commands: to register 0x20 (mref) write 0x 32 (the new value for mref). to register 0x60 (e2addr) write 0x20 (the address of the mref register). to register 0x61 (e2ctr l) write 0x03 (the command to copy the value to eeprom). wait 5ms. to register 0x61 (e2ctrl) write 0x00, to turn off eeprom access. result: the value 0x32, located in the mref register, is programmed into the eeprom and becomes the new power- up default value for mref. summary: 0x20 32 0x60 20 0x61 03 wait 5ms 0x61 00 e2ctrl provides additional functions beyond simply progra mming a register?s value into the eeprom. data may be transferred in either direction, from the registers to the eeprom, or from the eeprom to the registers. register data may be transferred into or out of the eeprom in groups of eight, a page at a time. the page address boundaries are predefined, and e2addr must be loaded with the address of the first byte of the page that is to be copied. page addresses begin at 0x00 and increment by eight, with the second page beginning at 0x08, the third at 0x10, etc. to program a full page of data into the eeprom, write the address of the page?s first byte to e2addr, and write 0x04 to e2ctrl. wait 5ms, and then end the write cycle by writing 0x00 to e2ctrl. when finished accessing the eeprom always write 0x00 to e2ctrl to bloc k inadvertent eeprom read/writes. table 12-2 on page 26 details the functions available through e2ctrl. table 12-2. eeprom address register (e2addr, 0x60), defaults highlighted . register address register data d7 d6 d5 d4 d3 d2 d1 d0 e2addr 0x60 - e2addr[6:0] default 00000000 eeprom minimum address 0x00 -0000000 eeprom maximum address 0x51 -1010001
27 msl2021 [datasheet] 42062a?led?02/2013 table 12-3. eeprom status regist er (e2ctrl, 0x61), defaults highlighted . 13. detailed register descriptions the msl2021 registers are summarized in ?control registers? on page 25 . detailed register information follows. 13.1 string duty cycle cont rol registers (sdcr18 thr ough sdcr80, 0x00 through 0x1f) holds the look-up table for the thermistor color-adjust string duty cycle correction. see ?light color and the thm input? on page 20 for information. put the device to sleep using sleep register 0x24 before modifying the sdcr values to avoid undesired changes in the light output of the leds. table 13-1. string duty cycle cont rol registers (sdcr18 through sdcr80, 0x00 through 0x1f), defaults highlighted 13.2 main string reference volt age register (mref, 0x20) holds the dac value that controls the reference voltage for the main string fet source feedback voltage. the reference voltage equals decimal value of this register times 2mv. the default value for msref is 0x64, which equates to ms ref = 200mv. register address register data d7 d6 d5 d4 d3 d2 d1 d0 e2ctrl 0x61 - - - - - rwctrl[2:0] default 00000000 eeprom read / write disabled xxxxx 000 read 1 byte from eeprom x x x x x 0 0 1 read 8 bytes from eeprom x x x x x 0 1 0 write 1 byte to eeprom x x x x x 0 1 1 write 8 bytes to eeprom x x x x x 1 0 0 unused x x x x x 1 0 1 x x x x x 1 1 x register name address register data d7 d6 d5 d4 d3 d2 d1 d0 sdcr18 through sdcr80 0x00 ? 0x1f sdcr[7:0] default (see table 11-2 on page 21 ) xxxxxxxx correction factor = 0 00000000 correction factor = 1 11111111
28 msl2021 [datasheet] 42062a?led?02/2013 table 13-2. main string reference register (mref, 0x20), defaults highlighted 13.3 color-adjust string reference voltage register (caref, 0x21) holds the dac value that controls the reference voltage fo r the color-adjust string fet source feedback voltage. the reference voltage equals decimal value of this register time s 2mv. the default value for ca sref is 0x64, which equates to ca ref = 200mv. table 13-3. color-adju st string reference register (caref, 0x21), defaults highlighted 13.4 fault disable register (fault, 0x22) bits d0 and d1 control the fault response for the color-adjust string. for fault response behavior see ?fault conditions? on page 15 . bit d2 prevents the thermal shutdown fault from pulling fl tb low. write 0x03 to this register to clear faults; write 0x00 to re-enable fault response. table 13-4. fault disable regist er (fault, 0x22), defaults highlighted register name address register data d7 d6 d5 d4 d3 d2 d1 d0 mref 0x20 mref[7:0] default: m ref = 100 * 2mv = 200mv 01100100 m ref = 0 ? 2mv = 0v 00000000 m ref = 255 * 2mv = 510mv 11111111 register name address register data d7 d6 d5 d4 d3 d2 d1 d0 caref 0x21 caref[7:0] default: v caref = 100 * 2mv = 200mv 01100100 v caref = 0 ? 2mv = 0mv 00000000 v caref = 255 ? 2mv = 510mv 11111111 register name address register data d7 d6 d5 d4 d3 d2 d1 d0 fault 0x22 - - - - - tsdmask ocdis scdis default 00000 0 1 1 act on faults xxxxx 0 0 0 disable led short circuit fault xxxxx x x 1 disable string open circuit fault xxxxx x 1 x do not allow thermal shutdown fault to pull fltb low xxxxx 1 x x
29 msl2021 [datasheet] 42062a?led?02/2013 13.5 fault status register (faultstat, 0x23), read only reports the fault status for the color-adjust string. when a faul t is reported in this register, the fault output fltb pulls lo w. toggle en low, then high to clear the faults. faults recur if the fault persists. table 13-5. fault status register (faultstat, 0x23), defaults highlighted 13.6 sleep register (sleep, 0x24) puts the device to sleep (the serial interface remains awake). when asleep, device supply current reduces to 7ma (typical), the gate drive outputs stop switching, and the leds turn off. table 13-6. sleep register (sleep, 0x24), defaults highlighted 13.7 thermistor temperature regi ster (temp, 0x31), read only reports the thermistor temperature at 2c per lsb. w hen the thermistor temperature is equal to or below 18 ? c, this register returns 0x12, or 18 ? c. when the thermistor temperature is equal to or above 80 ? c, this register returns 0x50, or 80 ? c. table 13-7. thermistor temperature re gister (temp, 0x31), defaults highlighted register name address register data d7 d6 d5 d4 d3 d2 d1 d0 faultstat 0x23 - - - - - tsd ocflt ssflt no faults detected xxxxxx 0 0 led short circuit fault detected xxxxxx x 1 string open circuit fault detected xxxxxx 1 x the msl2021 is in thermal shutdown xxxxx1 x x register name address register data d7 d6 d5 d4 d3 d2 d1 d0 sleep 0x24 - - - - - - - sleep default 0000000 0 device is awake x x x x x x x 0 device is asleep x x x x x x x 1 register name address register name d7 d6 d5 d4 d3 d2 d1 d0 temp 0x31 temp[7:0] minimum value: 0x12 = 18 ? c 0001001 0 maximum value: 0x50 = 80 ? c 0101000 0
30 msl2021 [datasheet] 42062a?led?02/2013 13.8 password verification registers (pwv(high) and pwv( low), 0x38 and 0x39) use these registers when locking the look-up table of t he msl2021. also, enter the password (chosen when the look-up table was locked) into these registers to allow reading the contents of a locked look-up table. see section ?msl2021 look-up table lockout procedure? on page 23 for details about locking the look-up table. table 13-8. password verification registers (pwv(high and pwv(low), 0x38 and 0x39), defaults highlighted 13.9 look-up table lock regi ster (lut lock, 0x3a) use this register to lock the look-up table of the msl2021. see section ?msl2021 look-up table lockout procedure? on page 23 for details about locking the look-up table. at power-up, this register returns 0x02 when the look-up table is locked, and returns 0x83 when the table is unlocked. table 13-9. look-up table lock regi ster (lut lock, 0x3a), defaults highlighted 13.10 efficiency optimi zer control regist er (eoctrl, 0x40) configures voltage feedback threshold for d. it is recommended that sleep = 1 (bit d0 in the configuration register 0x24) while changing this register to avoid perturbations of the string power supply. the msl2021 always performs a power supply voltage calibration when power is applied, en is taken high, or sleep is reset to 0. do not change bits d4 through d7. dthresh sets the voltage feedback threshold for d, the main string fet drain connection. d threshold = (dthresh ? 150mv) + 250mv. table 13-10. efficiency optimizer contro l register (fboctrl, 0x40), default highlighted register name address register name d7 d6 d5 d4 d3 d2 d1 d0 pwv(high) 0x38 password verification high byte [15:8] pwv(low) 0x39 password verifi cation low byte [7:0] default 111111 1 1 register name address register data d7 d6 d5 d4 d3 d2 d1 d0 lut lock 0x3a - - - - - -lock default 100000 1 1 locks the look-up table when committed to eeprom 000000 1 0 register name address / default register data d7 d6 d5 d4 d3 d2 d1 d0 fboctrl 0x40 - - - - dthresh[3:0] default = 0xe5 1 1 1 0 0 1 0 1 d threshold = (0 ? 150mv) + 250mv = 0.25v 1 1 1 0 0 0 0 0
31 msl2021 [datasheet] 42062a?led?02/2013 13.11 registers 0x60 a nd 0x61, eeprom access these registers control access to the eeprom. see ?eeprom and power-up defaults? and ?eeprom address and control/status registers? on page 26 for information. 13.12 password registers (pw(hi gh) and pw(low ), 0x68 and 0x69) use these registers to enter the password when locking the look-up table of the msl2021. see section ?msl2021 look- up table lockout procedure? on page 23 for details about locking the look-up table. table 13-11. password registers (pw(high) and pw(low), 0x68 and 0x69), defaults highlighted 14. i2c serial interface the msl2021 operates as a slave that sends and receives data through an i2c/smbus compatible 2-wire serial interface. the interface is not needed for operation, but is provided to allow control and monitoring of device functions. these functions include changing the look-up table and equati on parameters, changing the string current reference feedback voltages, reading and adjusting the fault response behavior and status, putting the device to sleep without losing the register settings, and programming the eeprom. t he i2c/smbus compatible interface is suitable for 100khz, 400khz and 1mhz communication. the interface uses data i/o sda and clock input scl to achieve bidirectional communication between master and slaves. fault output fltb opti onally alerts the host system to faults detected by the msl2021 ( figure 14-1 on page 32 and ?fault conditions? on page 15 ). during over temperature shutdown (tsd) the serial interface remains active. the master, typically a microcontroller, initiates all dat a transfers, and generates the clock that synchronizes the transfers. sda operates as both an input and an open-drai n output. scl operates only as an input, and does not perform clock-stretching. pull-up resistors are required on sda, scl and fltb. ??? ??? d threshold = (5 ? 150mv) + 250mv = 1v 1 1 1 0 0 1 0 1 ??? ??? d threshold = (15 ? 150mv) + 250mv = 2.5v x 1 1 0 1 0 1 1 register name address / default register data d7 d6 d5 d4 d3 d2 d1 d0 register name address register data d7 d6 d5 d4 d3 d2 d1 d0 pwv(high) 0x68 password high byte [15:8] pwv(low) 0x69 password low byte [7:0] default 111111 1 1
32 msl2021 [datasheet] 42062a?led?02/2013 figure 14-1. i 2 c interface connections a transmission consists of a start condition sent by a master, a 7-bit slave address plus one r/w bit, an acknowledge bit, none or many data bytes each separated by an acknowledge bit, and a stop condition ( figure 14-2 , figure 14-4 and figure 14-5 on page 33 ). figure 14-2. i 2 c serial interface timing details 14.1 i 2 c bus timeout the bus timeout feature allows the msl2021 to reset the serial bus interface if a communication ceases before a stop condition is sent. if scl or sda is low for more than 25m s (typical), then the msl2021 terminates the transaction, releases sda and waits for another start condition. 14.2 i 2 c bit transfer one data bit is transferred during each clock pulse. sda must remain stable while scl is high. figure 14-3. i 2 c bit transfer master (c) sda int scl sda fltb scl msl2021 v i2c 2 x 2.2k ? typical 100k ? start condition repeated start condition star t condition stop condition t hd : st a t r t f t high t low t su : dat t hd : dat t su : st a t hd : st a t su : sto t buf sd a scl sd a scl sda level stable sda data valid sda allowed to change level
33 msl2021 [datasheet] 42062a?led?02/2013 14.3 i 2 c start and stop conditions both scl and sda remain high when the interface is free. the master signals a transmission with a start condition (s) by transitioning sda from high to low while scl is high. w hen the master has finished communicating with the slave, it issues a stop condition (p) by trans itioning sda from low to high while scl is high. the bus is then free. figure 14-4. i 2 c start and stop conditions 14.4 i 2 c acknowledge bit the acknowledge bit is a clocked 9th bit which the recipient uses to handshake receipt of each byte of data. the master generates the 9th clock pulse, and the recipient holds sda low during the high period of the clock pulse. when the master is transmitting to the msl2021, the msl2021 pulls sda low because the msl2021 is the recipient. when the msl2021 is transmitting to the master, the master pulls sda low because the master is the recipient. figure 14-5. i 2 c acknowledge 14.5 i 2 c slave address the msl2021 has a 7-bit long slave address, 0b0100000, followed by an eighth bit, the r/w bit. the r/w bit is low for a write to the msl2021, high for a read from the msl2021. all msl2021 devices have the same slave address; when using multiple devices and communicating with them through their serial interfaces, make external provision to route the serial interface to the appropriate device. note that development systems that use i 2 c often left-shift the address one position before they insert the r/w bit, and so expect a default address of 0x20 (not 0x40). sda scl start condition stop condition s p sda transmitter scl start condition acknowledge by receiver s a sda receiver 12 891
34 msl2021 [datasheet] 42062a?led?02/2013 figure 14-6. i 2 c slave address 14.6 i 2 c message format for writ ing to the msl2021 a write to the msl2021 contains the msl2021?s slave address, the r/w bit cleared to 0, and at least 1 byte of information ( figure 14-7 on page 34 ). the first byte of information is the regi ster address byte. the register address byte is stored as a register pointer, and determines which register the following byte is written into. if a stop condition is detected after the register address byte is received, then the msl2021 takes no further action beyond setting the register pointer. figure 14-7. i 2 c writing a register pointer when no stop condition is detected, the byte transmitted afte r the register address byte is a data byte, and is placed into the register pointed to by the register address byte ( figure 14-8 ). to simplify writing to multiple consecutive registers, the register pointer auto-increments dur ing each following acknowledge period. further data bytes transmitted before a stop condition fill subsequent registers. figure 14-8. i 2 c writing two data bytes 14.7 i 2 c message format for reading from the msl2021 read the msl2021 registers using one of two techniques. the first technique begins the same way as a write, by setting the register address pointer as shown in figure 14-7 , including the stop condition (note that even though the final objective is to read data, the r/w bit is first sent as a write because the address pointer byte is being written into the device). follow the figure 14-7 transaction by what shown in figure 14-9 , with a new start condition and the slave address, this time with the r/w bit set to 1 to indicate a read. then, after the slave initiated acknowledge bit, clock out as many bytes as desired, separated by master initiated sda scl 1 2 3 4 5 6 7 8 9 a7 = 0 a a6 = 1 a5 = 0 a4 = 0 a3 =0 a2 = 0 a1 = 0 r / w msb sda 0 1 0 0000 0 a d7 d0 a acknowledge from msl202x start stop slave address, write access set register pointer to x ...... the register pointer now points to x; a subsequent read access reads from register address x acknowledge from msl202x sda 0 1 0 0000 0 a d7 d0 aa d0 a acknowledge from msl202x start stop slave address, write access set register pointer to x data writes to register x d7 ...... the register pointer now points to x + 2; a subsequent read access begins reading from register address x + 2 acknowledge from msl202x acknowledge from msl202x ...... d7 d0 ...... data writes to register x + 1 acknowledge from msl202x
35 msl2021 [datasheet] 42062a?led?02/2013 acknowledges. the pointer auto-increments during each master initiated acknowledge period. end the transmission with a not-acknowledge followed by a stop condition. figure 14-9. i 2 c reading register data with preset register pointer the second read technique is illustrated in figure 14-10 . write to the msl2021 to set the register pointer, send a repeated start condition after the second acknowledge bit, then send the slave address again with the r/w bit set to 1 to indicate a read. then clock out the data bytes separated by master initiated acknowledge bits. the register pointer auto-increments during each master initiated acknow ledge period. end the transmission with a not-acknowledge followed by a stop condition. this technique is recommended for buses with multiple masters, because the read sequence is performed in one uninterruptible transaction. figure 14-10. i 2 c reading register data using a repeated start 14.8 i 2 c message format for broadcast writing to multiple devices with a broadcast write to msl2021, a master broadcasts the same register data to all msl2021s on the bus. first send the broadcast write slave address of 0x00, followed by t he msl2021 broadcast device id of 0x42. these two bytes are followed by the register address in the msl2021s that the following data are to be written into, and finally the data byte(s) to be written into all devices. a broadcast write example is shown in figure 14-11 . here, the same register address in every msl2021 is written to with identical data. if further data bytes are transmitted before t he stop condition, they are stored in subsequent internal registers of each msl2021. sda 0 1 0 0000 1 a d7 d0 a d0 a acknowledge from msl202x start stop slave address, read access read register address x read register address x + 1 d7 ...... the register pointer now points to x + 2; a subsequent read access reads from register address x + 2 not acknowledge from master ...... acknowledge from master sda 0 1 0 0000 0 a repeated start d0 a 1 1 0000 1 a d0 a acknowledge from msl202x 0 start stop slave address write access slave address read access read registers d7 acknowledge from msl202x acknowledge from msl202x not acknowledge from master ...... d7 ...... set register pointer
36 msl2021 [datasheet] 42062a?led?02/2013 figure 14-11. i 2 c broadcast writing a data byte there is no broadcast read. however, a broadcast write may be used to set up the internal register pointers of all the msl2021s in a system to speed up the subsequent individual reading of, for example, all the status registers. figure 14- 12 illustrates a broadcast write that sets all the register pointers, and issues a stop. figure 14-12. i 2 c broadcast writing a register pointer sda 00 000000 a 00 a d0 a acknowledge from msl202x start stop broadcast write slave address msl202x broadcast id sets all register pointers to x data writes to all register xs d7 100001 all register pointers now point to x + 1; the first subsequent read access of each msl202x reads from register address x + 1 acknowledge from msl202x ...... d0 a d7 ...... acknowledge from msl202x acknowledge from msl202x sda 00 000000 a 00 a d0 a acknowledge from msl202x start stop broadcast write slave address msl202x broadcast id sets all register pointers to x d7 100001 all register pointers now point to x; the first subsequent read access of each msl202x begins reading from register address x ...... acknowledge from msl202x acknowledge from msl202x
37 msl2021 [datasheet] 42062a?led?02/2013 15. packaging information no representation or warranties are made concerning third-party patents with regard to the use of atmel ? products. the mixing of red leds with phosphor-converted leds may be protect ed by certain third-party patents, such as u.s. patent no. 7,213,940 and related patents of cree, inc. drawing no. rev. title gpc 24m1 b zuh package drawing contact: packagedrawings@atmel.com 1/10/13 symbol min nom max note a a1 b d d2 e e2 e l common dimensions (unit of measure=mm) - 0.00 0.20 2.35 2.35 0.35 0.85 - 0.25 4.00 bsc 2.45 4.00 bsc 2.45 0.50 bsc 0.40 0.90 0.05 0.30 2.55 2.55 0.45 2 1. refer to jedec drawing mo-220 (saw singulation) 2. dimension "b" applies to metalized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. (top view) d e (side view) (bottom view) k0.20 -- 24 a3 0.203 ref a a1 (a3) pin 1 id 1 2 0.08 seating plane d2 e2 24x l 24x b e/2 e k d 0.1 c d 0.1 c d 0.1 c notes: d 24m1 , 24-lead, 4.0x4.0x0.9mm body, 0.50mm pitch, 2.45mm sq exposed pad, very thin fine pitch, quad flat no lead package (vqfn)
38 msl2021 [datasheet] 42062a?led?02/2013 16. datasheet revision history 16.1 42062a ? 02/2013 1. initial revision.
i msl2021 [datasheet] 42062a?led?02/2013 table of contents features 1 typical applications 1 1. introduction 2 2. ordering information 2 3. application circuit 2 4. absolute maximum ratings 3 5. electrical characteristics 4 6. block diagram 11 7. pinout and pin description 12 7.1 pinout msl2021 12 7.2 pin descriptions 12 8. typical application circuit 14 9. detailed description 14 10. fault conditions 15 11. applications information 15 11.1 turn-on sequence 15 11.2 setting the main string current with rs 15 11.3 setting ac/dc output voltage 16 11.4 selecting the main string mosfet 16 11.5 selecting the drain resistor ? rd 16 11.6 selecting the color-adjust string floating buck components 17 11.7 pwm and led brightness 20 11.8 light color and the thm input 20 11.9 msl2021 look-up table lockout procedure 23 11.9.1 example: 23 12. control registers 25 12.1 eeprom and power-up defaults 26 12.2 eeprom address and cont rol/status registers 26 13. detailed register descriptions 27 13.1 string duty cycle control registers (s dcr18 through sdcr80, 0x00 through 0x1f) 27 13.2 main string reference volt age register (mref, 0x20) 27 13.3 color-adjust string reference voltage register (caref, 0x21) 28 13.4 fault disable register (fault, 0x22) 28 13.5 fault status register (faultstat, 0x23), read only 29 13.6 sleep register (sleep, 0x24) 29 13.7 thermistor temperature register (temp, 0x31), read only 29 13.8 password verification registers (pwv(high) and pwv(low), 0x38 and 0x39) 30 13.9 look-up table lock register (lut lock, 0x3a) 30
ii msl2021 [datasheet] 42062a?led?02/2013 13.10 efficiency optimizer contro l register (eoctrl, 0x40) 30 13.11 registers 0x60 and 0x61, eeprom access 31 13.12 password registers (pw(high) and pw(low), 0x68 and 0x69) 31 14. i2c serial interface 31 14.1 i2c bus timeout 32 14.2 i2c bit transfer 32 14.3 i2c start and stop conditions 33 14.4 i2c acknowledge bit 33 14.5 i2c slave address 33 14.6 i2c message format for writing to the msl2021 34 14.7 i2c message format for reading from the msl2021 34 14.8 i2c message format for broadcast writing to multiple devices 35 15. packaging information 37 16. datasheet revision history 38 16.1 42062a ? 01/2013 38 table of contents i
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